Wafer joining technology can be used to integrate different materials with various properties into one compact process-compatible material system. The technology has great potential to innovate the current high technology industries. For example, joining GaAs or InP-based materials to other semiconductor materials can result in the integration of optical, photovoltaic, and electronic devices and enhance the performance of computers, solar cells, light emitting diodes and other electronic devices.
One of the limitations in Group III-V semiconductor devices, such as multijunction solar cells, is incorporating Group III-V layers with desirable bandgap combination into a device that is lattice-matched with the growth substrate. This severely limits the choice of bandgaps that can be incorporated into the device and thus prevents the fabrication of devices with optimal performance. It is hence desirable to develop a method that allows integration of devices grown on different substrates so that the lattice matching constraints with the growth substrate can be reduced.
Existing solutions such as the growth of lattice-mismatched (metamorphic) layers, mechanical stacking, and indirect wafer bonding have been used. In the metamorphic approach, a buffer layer with controlled gradient in the lattice constant is grown between the substrate and the desired metamorphic layer. In the indirect wafer bonding approach, devices are grown on different substrates having different lattice constants, and a dielectric or metal layer is deposited upon the top surface of the devices. The devices are then integrated mechanically or electrically via wafer bonding. One or both of the substrates may be eventually removed.
In the metamorphic approach, the introduction of a buffer layer with a controlled adjustment in lattice constant can introduce high densities of defects, and may lead to the growth of non-optimal quality device layer reducing device performance. In the indirect wafer bonding approach, the bonding is done via deposition of an adhesion layer, e.g. SiO2, Si3N4, other dielectrics, metal oxides, metals etc. on individual wafers prior to bonding (called indirect bonding). Although it does not necessitate high temperature annealing, the SiO2, Si3N4, and metal oxides etc ‘bonding layers’ are insulating, which does not allow monolithic electrical integration of the bonded devices. On the other hand, indirect bonding using metal layers as bonding interlayers make the bonded interface optically opaque, preventing optical integration of the devices on the opposite sides of the bonded interface. In the prior art of direct bonding, the direct bonded interface needs to be annealed at high temperatures (typically exceeding 500° C.) for a significant period of time (typically few hours) to obtain a mechanically robust interface with low electrical resistance. Such high temperature annealing for prolonged periods of time will often lead to reduced performance in many devices.
The existing semiconductor-semiconductor direct bonding solution between GaAs and InP materials suffers from low bond strength unless annealed at high temperatures (>500° C.) for extended periods of time. The existing indirect bonding solutions do not allow both electrically conductive and optically transparent integration across the indirect bonded interface.
There exists a need for an improved method for directly bonding semiconductor wafers that improves the mechanical integrity, optical transparency, and electrical resistance at the bond interfaces to achieve an increase in power output, efficiency, performance, and cost effectiveness.